Nikhil Jayakumar

Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar 2010 edition

Marc Notes: Title from content provider.; Access is restricted to subscribing institutions. Jacket Description/Back: Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes). Table of Contents: 1. Introduction -- 1.1. The Need for Low Power Design -- 1.2. Leakage and Its Contribution to IC Power Consumption -- 1.3. Summary -- References -- Part I. Leakage Reduction Techniques: Minimizing Leakage in Modem Day DSM Processes -- 2. Existing Leakage Minimization Approaches -- 2.1. Leakage Minimization Approaches: An Overview -- 2.1.1. Power Gating/MTCMOS -- 2.1.2. Body Biasing/VTCMOS -- 2.1.3. Input Vector Control -- 2.2. Summary -- References -- 3. Computing Leakage Current Distributions -- 3.1. Overview -- 3.2. Introduction -- 3.3. Background -- 3.3.1. Reduced Ordered Binary Decision Diagrams -- 3.3.2. Algebraic Decision Diagrams -- 3.4. The Intuition Behind Our Approach -- 3.5. Related Previous Work -- 3.6. Our Approach -- 3.6.1. Exact Computation of the Leakages of All Vectors -- 3.6.2. Approximate Computation of Leakages of All Vectors -- 3.7. Experimental Results -- 3.8. Summary -- References -- 4. Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- 4.1. Overview -- 4.2. Introduction -- 4.3. The Intuition Behind Our Approach -- 4.4. Related Previous Work -- 4.5. Our Approach -- 4.5.1. Computing Signal Probabilities -- 4.5.2. Finding the Best Leakage Candidate -- 4.5.3. Finding Best Leakage State for Selected Gate -- 4.5.4. Accepting Leakage States and Final MLV Determination -- 4.6. Experimental Results -- 4.6.1. Selecting Parameter Values for MLVC and MLVC-VAR -- 4.6.2. Comparing MLVC with Existing Techniques -- 4.6.3. Comparing MLVC-VAR with MLVC and RVA -- 4.7. Summary -- References -- 5. The HL Approach: A Low-Leakage ASIC Design Methodology -- 5.1. Overview -- 5.2. Philosophy of the HL Approach -- 5.3. Related Previous Work -- 5.4. The HL Approach -- 5.4.1. Design Methodology -- 5.4.2. Advantages and Disadvantages of the HL Approach -- 5.5. Experimental Results -- 5.5.1. Comparison of Placed and Routed Circuits -- 5.6. Using Gate Length Biasing Instead of VT Change -- 5.7. Leakage Reduction in Domino Logic -- 5.8. Summary -- References -- 6. Simultaneous Input Vector Control and Circuit Modification -- 6.1. Overview -- 6.2. Introduction -- 6.3. The Intuition Behind Our Approach -- 6.4. Related Previous Work -- 6.5. Our Approach -- 6.5.1. The Gate Replacement Algorithm -- 6.6. Experimental Results -- 6.7. Summary -- References -- 7. Optimum Reverse Body Biasing for Leakage Minimization -- 7.1. Overview -- 7.2. Goal and Background -- 7.3. Related Previous Work -- 7.4. Leakage Monitoring/Self-Adjusting Scheme -- 7.4.1. Leakage Current Monitoring Block (LCM) -- 7.4.2. Digital Control Block -- 7.5. Summary -- References -- 8. Part I: Conclusions and Future Directions -- References -- Part II. Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- 9. Exploiting Leakage: Sub-threshold Circuit Design -- 9.1. Overview -- 9.2. Introduction -- 9.2.1. The Opportunity -- 9.3. Summary -- References -- 10. Adaptive Body Biasing to Compensate for PVT Variations -- 10.1. Overview -- 10.2. Related Previous Work -- 10.3. Preliminaries: PLAs -- 10.3.1. PLA Design -- 10.3.2. PLA Operation -- 10.4. The Adaptive Body Biasing Solution -- 10.4.1. Self-Adjusting Bulk-Bias Circuit -- 10.5. Experimental Results -- 10.6. Loop Gain of the Adaptive Body Biasing Loop -- 10.7. Summary -- References -- 11. Optimum VDD for Minimum Energy -- 11.1. Overview -- 11.2. Introduction -- 11.3. Related Previous Work -- 11.4. Preliminaries -- 11.4.1. Operation of the PLA -- 11.4.2. Some Definitions -- 11.5. Experiments -- 11.5.1. Energy Estimation for a Circuit of PLAs -- 11.6. Summary -- References -- 12. Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- 12.1. Overview -- 12.2. Our Approach -- 12.2.1. Asynchronous Micropipelined NPLAs -- 12.2.2. Synthesis of Micropipelined PLA Networks -- 12.2.3. Circuit Details of PLAs and Stutter Blocks -- 12.3. Experimental Results -- 12.4. Optimum VDD for Micropipelined NPLAs -- 12.5. Summary -- References -- 13. Part II: Conclusions and Future Directions -- References -- Part III. Design of a Sub-threshold BFSK Transmitter IC -- 14. Design of the Chip -- 14.1. Overview -- 14.2. Test Vehicle -- 14.2.1. BFSK Radio Transmitter Architecture -- 14.3. System Architecture -- 14.3.1. PLA Basics -- 14.3.2. Network of PLA Operation -- 14.3.3. Dynamic Compensation Circuit -- 14.3.4. The Digital BFSK Modulator -- 14.3.5. Digital to Analog Converter -- 14.3.6. Common Source Amplifier -- 14.3.7. Antenna -- 14.4. Design Specifications -- 14.4.1. Link Budget Analysis -- 14.5. Summary -- References -- 15. Implementation of the Chip -- 15.1. Overview -- 15.2. Design Flow -- 15.3. HDL to Netlist Flow -- 15.4. SPICE Verification of Dynamic Compensation -- 15.5. DAC and Amplifier Design -- 15.6. Special Considerations -- 15.6.1. Testability and Redundancy -- 15.6.2. Voltage Domains -- 15.7. Standard Cell-Based BFSK Design -- 15.8. IO Pad and ESD Diode Design -- 15.9. Chip Integration and Pin-out -- 15.10. Layout -- 15.11. Summary of Verification Methodologies -- 15.12. Summary -- References -- 16. Experimental Results -- 16.3. Overview -- 16.2. Functional Verification -- 16.3. Dynamic Compensation Circuit -- 16.4. Operating Ranges -- 16.5. Spectrum of Output Sinusoidal Signals -- 16.6. Comparison with Standard Cells -- 16.7. Summary -- Reference -- Summary and Future Work -- Conclusion -- Index. Publisher Marketing: Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.