Chunjie Duan

On and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan 2010 edition

Marc Notes: Title from content provider.; Access is restricted to subscribing institutions. Jacket Description/Back: On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford. Table of Contents: Part I. On-Chip Crosstalk and Avoidance -- 1. Introduction of On-Chip Crosstalk Avoidance -- 1.1. Challenges in Deep Submicron Processes -- 1.2. Overview of On-Chip Crosstalk Avoidance -- 1.3. Bus Encoding for Crosstalk Avoidance -- 1.4. Part I Organization -- 2. Preliminaries to On-Chip Crosstalk -- 2.1. Modeling of On-Chip Interconnects -- 2.2. Crosstalk Based Bus Classification -- 2.3. Bus Encoding for Crosstalk Avoidance -- 2.4. Notation and Terminology -- 3. Memoryless Crosstalk Avoidance Codes -- 3.1. 3C-FreeCACs -- 3.1.1. Forbidden Pattern Free CAC -- 3.1.2. Forbidden Transition Free CAC -- 3.1.3. Circuit Implementation and Simulation Results -- 3.2. 2C-FreeCACs -- 3.2.1. Code Construction -- 3.2.2. Code Cardinality and Area Overhead -- 3.2.3. 2C Experiments -- 3.3. lC-Free Busses -- 3.3.1. Bus Configurations -- 3.3.2. Experimental Results -- 3.4. Summary -- 4. CODEC Designs for Memoryless Crosstalk Avoidance Codes -- 4.1. Bus Partitioning Based CODEC Design Techniques -- 4.2. Group Complement -- 4.2.1. Proof of Correctness -- 4.3. Bit Overlapping -- 4.4. FPF-CAC CODEC Design -- 4.4.1. Fibonacci-Based Binary Numeral System -- 4.4.2. Near-Optimal CODEC -- 4.4.3. Optimal CODEC -- 4.4.4. Implementation and Experimental Results -- 4.5. FTF-CAC CODEC Design -- 4.5.1. Mapping Scheme -- 4.5.2. Coding Algorithm -- 4.5.3. Implementation and Experimental Results -- 4.6. Summary -- 5. Memory-based Crosstalk Avoidance Codes -- 5.1. A 4C-Free CAC -- 5.1.1. A 4C-free Encoding Technique -- 5.1.2. An Example -- 5.2. Codeword Generation by Pruning -- 5.3. Codeword Generation Using ROBDD -- 5.3.1. Efficient Construction of Gmkc-free -- 5.3.2. An Example -- 5.3.3. Finding the Effective kC Free Bus Width from Gmkc-free -- 5.3.4. Experimental Results -- 5.4. Summary -- 6. Mulli-Valued Logic Crosstalk Avoidance Codes -- 6.1. Bus Classification in Multi-Valued Busses -- 6.2. Low Power and Crosstalk Avoiding Coding on a Ternary Bus -- 6.2.1. Direct Binary-Ternary Mapping -- 6.2.2. 4X Ternary Code -- 6.2.3. 3X Ternary Code -- 6.3. Circuit Implementations -- 6.4. Experimental Results -- 6.5. Summary -- 7. Summary of On-Chip Crosstalk Avoidance -- Part II. Off-Chip Crosstalk and Avoidance -- 8. Introduction to Off-Chip Crosstalk -- 8.1. The Role of IC Packaging -- 8.2. Noise Sources in Packaging -- 8.2.1. Inductive Supply Bounce -- 8.2.2. Inductive Signal Coupling -- 8.2.3. Capacitive Bandwidth Limiting -- 8.2.4. Capacitive Signal Coupling -- 8.2.5. Impedance Discontinuities -- 8.3. Performance Modeling and Proposed Techniques -- 8.3.1. Performance Modeling -- 8.3.2. Optimal Bus Sizing -- 8.3.3. BusEncoding -- 8.3.4. Impedance Compensation -- 8.4. Advantages Over Prior Techniques -- 8.4.1. Performance Modeling -- 8.4.2. Optimal Bus Sizing -- 8.4.3. BusEncoding -- 8.4.4. Impedance Compensation -- 8.5. Broader Impact of This Monograph -- 8.6. Organization of Part II of this Monograph -- 9. Package Construction and Electrical Modeling -- 9.1. Level 1 Interconnect -- 9.1.1. Wire Bonding -- 9.1.2. Flip-Chip Bumping -- 9.2. Level 2 Interconnect -- 9.2.1. Lead Frame -- 9.2.2. Array Pattern -- 9.3. Modern Packages -- 9.3.1. Quad Flat Pack with Wire Bonding -- 9.3.2. Ball Grid Array with Wire Bonding -- 9.3.3. Ball Grid Array with Flip-Chip Bumping -- 9.4. Electrical Modeling -- 9.4.1. Quad Flat Pack with Wire Bonding -- 9.4.2. Ball Grid Array with Wire Bonding -- 9.4.3. Ball Grid Array with Flip-Chip Bumping -- 10. Preliminaries and Terminology -- 10.1. Bus Construction -- 10.2. Logic Values and Transitions -- 10.3. Signal Coupling -- 10.3.1. Mutual Inductive Signal Coupling -- 10.3.2. Mutual Capacitive Signal Coupling -- 10.4. Return Current -- 10.5. Noise Limits -- 11. Analytical Model for Off-Chip Bus Performance -- 11.1. Package Performance Metrics -- 11.2. Converting Performance to Risetime -- 11.3. Converting Bus Performance to di/dt and dv/dt -- 11.4. Translating Noise Limits to Performance -- 11.4.1. Inductive Supply Bounce -- 11.4.2. Capacitive Bandwidth Limiting -- 11.4.3. Signal Coupling -- 11.4.4. Impedance Discontinuities -- 11.5. Experimental Results -- 11.5.1. Test Circuit -- 11.5.2. Quad Flat Pack with Wire Bonding Results -- 11.5.3. Ball Grid Array with Wire Bonding Results -- 11.5.4. Ball Grid Array with Flip-Chip Bumping Results -- 11.5.5. Discussion -- 12. Optimal Bus Sizing -- 12.1. Package Cost -- 12.2. Bandwidth Per Cost -- 12.2.1. Results for Quad Flat Pack with Wire Bonding -- 12.2.2. Results for Ball Grid Array with Wire Bonding -- 12.2.3. Results for Ball Grid Array with Flip-Chip Bumping -- 12.3. Bus Sizing Example -- 13. Bus Expansion Encoder -- 13.1. Constraint Equations -- 13.1.1. Supply Bounce Constraints -- 13.1.2. Signal Coupling Constraints -- 13.1.3. Capacitive Bandwidth Limiting Constraints -- 13.1.4. Impedance Discontinuity Constraints -- 13.1.5. Number of Constraint Equations -- 13.1.6. Number of Constraint Evaluations -- 13.2. Encoder Construction -- 13.2.1. Encoder Algorithm -- 13.2.2. Encoder Overhead -- 13.3. Decoder Construction -- 13.4. Experimental Results -- 13.4.1. 3-Bit Fixed di/dt Example -- 13.4.2. 3-Bit Varying di/dt Example -- 13.4.3. Functional Implementation -- 13.4.4. Physical Implementation -- 13.4.5. Measurement Results -- 14. Bus Stuttering Encoder -- 14.1. Encoder Construction -- 14.1.1. Encoder Algorithm -- 14.1.2. Encoder Overhead -- 14.2. Decoder Construction -- 14.3. Experimental Results -- 14.3.1. Functional Implementation -- 14.3.2. Physical Implementation -- 14.3.3. Measurement Results -- 14.3.4. Discussion -- 15. Impedance Compensation -- 15.1. Static Compensator -- 15.1.1. Methodology -- 15.1.2. Compensator Proximity -- 15.1.3. On-Chip Capacitors -- 15.1.4. On-Package Capacitors -- 15.1.5. Static Compensator Design -- 15.1.6. Experimental Results -- 15.2. Dynamic Compensator -- 15.2.1. Methodology -- 15.2.2. Dynamic Compensator Design -- 15.2.3. Experimental Results -- 15.2.4. Dynamic Compensator Calibration -- 16. Future Trends and Applications -- 16.1. The Move from ASICs to FPGAs -- 16.2. IP Cores -- 16.3. Power Minimization -- 16.4. Connectors and Backplanes -- 16.5. Internet Fabric -- 17. Summary of Off-Chip Crosstalk Avoidance -- References -- Index. Publisher Marketing: Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is crosstalk, which becomes significant with shrinking feature sizes of VLSI fabrication processes. The presence of crosstalk greatly limits the speed and increases the power consumption of the IC design. This book focuses on crosstalk avoidance with bus encoding, one of the techniques that selectively mitigates the impact of crosstalk and improves the speed and power consumption of the bus interconnect. This technique encodes data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption.