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Direct Transistor-Level Layout for Digital Blocks Prakash Gopalakrishnan 2004 edition
Direct Transistor-Level Layout for Digital Blocks
Prakash Gopalakrishnan
The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
125 pages, 38 black & white illustrations, biography
| Medios de comunicación | Libros Hardcover Book (Libro con lomo y cubierta duros) |
| Publicado | 17 de junio de 2004 |
| ISBN13 | 9781402076657 |
| Editores | Springer-Verlag New York Inc. |
| Páginas | 125 |
| Dimensiones | 156 × 232 × 9 mm · 367 g |
| Lengua | Inglés |