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Applied Formal Verification: for Digital Circuit Design Douglas L. Perry
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Applied Formal Verification: for Digital Circuit Design
Douglas L. Perry
Formal verification is a digital design method. This tutorial shows designers how to apply Formal Verification, along with hardware description languages like Verilog and VHDL, to solve real-world design problems.
240 pages, 75 illustrations
| Medios de comunicación | Libros Hardcover Book (Libro con lomo y cubierta duros) |
| Publicado | 1 de mayo de 2005 |
| ISBN13 | 9780071443722 |
| Editores | McGraw-Hill Education - Europe |
| Páginas | 240 |
| Dimensiones | 154 × 231 × 23 mm · 512 g |
| Lengua | Inglés |
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